The present invention relates to a running speed detector of the digital type which detects the running speed by counting pulses having a frequency which is directly proportional to the running speed of a rotary member.
FIG. 1 shows a conventional running speed detector of this type. In FIG. 1, a pulse train 1 is produced by a pulse encoder (or shaft encoder) attached to the rotary shaft of a rotary member, and has a frequency which is proportional to the number of revolutions of the rotary member. Reference numeral 2 denotes a counter N which counts the number of pulses of the pulse train, numeral 3 denotes a register which stores the counted value n, i.e., the number of pulses counted by the counter N, numeral 4 denotes a counter T which counts the number of clock signals c of a predetermined frequency inputted thereto, numeral 5 denotes a register which stores the counted value Tn, i.e., which stores the number of clock signals counted by the counter 4, numeral 6 denotes a timing pulse generator which sends reset signals RS to the counters N and T, and which also sends latch signals RA to the registers 3 and 5. Reference numeral 7 denotes an arithmetic unit such as a microprocessor which reads the counted values n and Tn in the registers 3 and 5, respectively, in order to calculate a running speed V of the rotary member.
The operation of the running speed detector will be described herebelow with reference to FIG. 2, in which (a) denotes a pulse train 1, symbols P.sub.1, P.sub.2, . . . , Pn denote pulse numbers, and (b) denotes the change in the number of pulses n as a function of time.
The counters N and T initiate the counting operation from a time t.sub.O at which the pulse train 1 and a clock signal c are brought into synchronism with each other. The synchronization is effected by the reset signal RS. As the counted value of the counter T reaches T.sub.c at the time, t.sub.c the timing pulse generator 6 generates a reset signal RS and a latch signal RA at a time t.sub.n at which the period of a pulse pn in the pulse train 1 finishes. Responsive to the latch signal RA, the register 3 stores the counted value n counted by the counter N, and the register 5 stores the counted value Tn (sampling period) counted by the counter T from the time t.sub.0 to the time t.sub.n. At the same time, the counters N and T initiate the counting operation again responsive to the reset signal RS. Relying upon the counted values n and T.sub.n, the arithmetic unit 7 calculates EQU V=K.multidot.n/Tn (1)
to detect the running speed of the rotary member.
Here, Tc is a factor which induces error in the measurement. When a maximum allowance is denoted by .alpha., therefore, Tc must be so set as to satisfy a relation .alpha.&gt;1/Tc.
According to the above-mentioned conventional speed detecting method, therefore, it is not possible to decrease the sampling period Tn to be smaller than Tc. Namely, the running speed of the rotary member can only be detected after n pulses in the pulse train have been counted. In controlling the running speed of, for example, the motor, therefore, the speed of control response is limited by Tc.